Process variations, such as mask errors in lithography and die fabrication, occur during manufacturing one batch of chips and another batch of chips, resulting in overdoping or underdoping of the components in that batch. When a batch is overdoped, it produces transistors with more current capacity because it has more carriers. These are called strong transistors because they can sink more current than the designer desired. On the other hand, an underdoped batch may result in weaker transistors because they may sink less current than the design anticipated.
“Process corner” refers to a set of conditions related to manufacturing process of an integrated circuit. Several process corners are possible, including, fast process corner, slow process corner, n-fast/p-slow corner and p-fast/n-slow corner. The transistors in a fast process corner are strong, that is, they sink more current than the design anticipated. A fast process corner produces a highest acceptable transconductance value for a transistor of a given size. On the other hand, in a slow process corner, the transistors are weak and sink less current than anticipated, and the transistors of a given size have the lowest acceptable transconductance value. In an n-fast/p-slow process corner, the N-MOS transistors sink more current than the designer anticipated, while the P-MOS transistors sink less current than expected by the design. Similarly, in a p-fast/n-slow process corner, the N-MOS sink relatively less current, while the P-MOS transistors sink relatively more current than was anticipated by the circuit design.
In a PLL, if the output frequency of a controlled oscillator (CO) is plotted against input control voltage across different corner, each corner may appear at a different slope representing different gain. But the goal is to deliver the necessary frequency range across all process corners. To achieve this result, a circuit must have more gain than optimal, that is, more gain than would be needed if process variations were not an issue. Alternatively, the power in a fast process corner may have to be reduced to nearly the same as in a slow process corner. In general, a designer configures the circuit with more gain to ensure that the full frequency range is delivered even in case of a slow process corner. A PLL so designed must operate in a stable manner in case of a fast process corner where a DCO may have more gain than the optimal solution.
One method of managing process variations is to add capacitive loads between stages and thereby creating a number of stages. Another method is to use a parallel path to change drive strength of stages. Other methods require a bias generator block but that complicates the design. Moreover, starting up a DCO with bias generator block may take time unless the bias block was always turned on, but this may not be suitable for applications where power consumption must be kept low when the DCO is stopped. All other methods, therefore, may achieve the desired frequency control, but inefficient as to power consumption or have poor starting characteristics. Accordingly there is identified a need for an improvement in the art.